I can’t believe we’re talking Angstroms already.
TSMC: <a href="https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_A14" rel="nofollow">https://www.tsmc.com/english/dedicatedFoundry/technology/log...</a><p>Not sure what this source is, but it looks sketchy.
IEDM is more or less the most prestigious conference on semiconductor devices. Hard to get a more reliable source than a TSCM-affiliated paper from IEDM.
The source is the IEDM conference website where TSMC will be presenting the paper in Dec 2026
Chip density increase is slowing down. Since N10, density scaling has been 60-80%. N3 to N2 is only 20%. And now N2 to A14 is also only 20%.
Yes but considering N10 was fabricated with DUV lithography right before the shift to EUV I'm not sure how fair that comparison is. That being said the density scaling of N10 nodes compared to predecessors using the same lithography technique was much higher than we have seen since with the EUV nodes. Density scaling is the most meaningful comparison metric, but it doesn't take into account additional technology developments.
20% growth then 20% again still seems pretty good to me though. I guess compounded that is a 44% increase N3 to A14 which also starts to look much better if you zoom out a bit. I mean 44% more density since a few years ago seems, if not massive, not insignificant, like you will definitely notice it.
Between N2 and A14 should sit A16.
Is the increase in wafer cost higher than the density increase? If so, that means that the cost per transistor is also going up.
It's hard to tell because AI has pushed up costs. IE. Chip fab margins are increasing.<p>But generally, I think it's even or increasing $/transistor for each node. I'd guess that A14 would have been 20% more expensive than N2 regardless or AI or not.<p>It probably is still worth it because you're also getting 20-30% better power efficiency - which is a big deal for data center chips.
A lot of that is the lack of SRAM scaling. There’s still quite a bit of improvements in the back end (metal traces). That aside, if foundries adopted say a 1T-1C SRAM we’d see a pretty rapid density doubling
Is 1T1C SRAM a technological thing or does it mean "persuade designers to use DRAM in the many cases where the retention contract could be timeboxed with a bit of extra thought and cross-team haggling"?
> 1T-1C SRAM<p>Aka eDRAM? It was a thing back on 14nm node, but AFAIR not so much anymore. The 1C part is hard to get right in a way that is compatible with a logic process.
MRAM is 1T, non-volatile and supposedly has nanosecond-scale write times so it naively seems like it'd be an ideal SRAM replacement. But I guess shrinking MTJ is more difficult than other components or there are some other limitations.
In simpler terms, the SRAM density improved by 2.9% (according to ChatGPT). Which is better than it sounds, because SRAM had reached a wall, in terms of density gains, and, chips can be dominated by SRAM in terms of surface area, so this can mean a lot more room for logic, even though that is also getting considerably denser.
Come on we're in the 21st century, UTF-8 is pervasive. Just call it "Å14" node.
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