I miss itanium. I feel like a madman for saying it, but I do. Something about it is just alluring to me. Alas, the problems were too hard to solve or weren't worth solving anymore<p>Ironically, it died around the time LLMs/AI started becoming good. I feel like the compiler problems with vliw could be solved to a degree with a purpose built ai
So I feel like I need to write a blog post about this, but succinctly I think there's a good argument to be made that the issue wasn't the compiler despite popular wisdom. I don't even think it was the nature of unpredictable memory access times either as the itanium has a ton of special architectural hardware to handle unpredictable memory accesses (a lot of which are essentially some of the primitives that an OoO core uses for internal bookkeeping, just exposed architecturally).<p>I just think the arch has a similarity to archs like cell where it was planned for a world without the end of dennard scaling and just stopped making sense when we weren't targeting scaling to 10Ghz consumer CPUs and beyond.<p>The relatively fixed clock period that makes sense post ~2006 also means that the CPU architecture of that made the most sense ~2006 (Tomasulo OoO cores) continues to make sense, with most of the process gains going to just making bigger, wider cores.
It was also planned for a world where high-end CPUs were differentiated by their ability to run floating-point-heavy workloads with relatively predictable memory access patterns.<p>The rise of the web—and databases behind it—as the dominant high-end, high-margin workload obsoleted that assumption.<p>There’s a great presentation floating around where a Compaq-acquired-DEC engineer is trying to justify how great the OpenVMS port from Alpha to Itanium is going, despite benchmarks showing Alpha smoking Itanium running Apache.
If only the Alpha had hung on.
I worked for a company that had a fairly large OpenVMS installation and had to make the transition from Alpha to Itanium. It required a considerable amount of work and the early iterations of Itanium did not provide a clear performance improvement over the final Alpha EV7z that we had been using in some GS1280s.<p>Going by my faulty memory, I'd say it wasn't until Tukwila that it was a clear win over Alpha EV7z. By the time Tukwila arrived, it was pretty clear that Itanium's goose was already cooked.
I recall opening up the Itanium manual, and by the end of the architecture description, just despairing of the thought of trying to write a compiler for it. Itanium, I think, was ultimately a victim of its weirdness: it's too weird to really comfortably write assembly by hand; the compilers weren't really capable with its weirdness, so "regular" code was worse off than you'd normally expect. Raymond Chen has pointed out in several articles how the hardware took advantage of C's UB to do some really weird things--and this is an era where most developers expected UB to really be just implementation-defined behavior.<p>Combine that with the fact that the hardware development process seems to have been compromised from the start (if you told me the hardware architects never looked at anything other than 30-instruction traces of BLAS kernels, I'd believe you), and the insane hype that was built up for it... it's not surprising that it had an extremely underwhelming launch.
I wonder if most people kept them around just so they don't have to port their apps or migrate to something new.<p>I worked at an HP shop, and Itanium ran HP/UX so they kept running their business on their PickBASIC (and whatever database that I've forgotten the name of) system
There was also a long piece by a former Intel chip designer who was incredulous about how much the Itanium team was promising numbers based on a very few hand-scheduled routines for FPU-limited code. I think there’s a solid argument that the design just wasn’t based on a correct understanding of what most CPUs did and over-indexed on the most performance-sensitive HPC code. I once helped run some HPC code on a test Itanium system and even there it was just so easy to fall out of the only patterns which performed well and end up slower than older Pentiums even before factoring price into the evaluation.<p>> I said, wait I am sorry to derail this meeting. But how would you use a simulator if you don't have a compiler? He said, well that's true we don't have a compiler yet, so I hand assembled my simulations. I asked "How did you do thousands of line of code that way?" He said “No, I did 30 lines of code”. Flabbergasted, I said, "You're predicting the entire future of this architecture on 30 lines of hand generated code?" [chuckle], I said it just like that, I did not mean to be insulting but I was just thunderstruck. Andy Grove piped up and said "we are not here right now to reconsider the future of this effort, so let’s move on".<p><a href="https://www.sigmicro.org/media/oralhistories/colwell.pdf" rel="nofollow">https://www.sigmicro.org/media/oralhistories/colwell.pdf</a><p>> Davidson also pointed out two areas where academic research could create a blind spot for architecture developers. First, most contemporary academic research ignored CISC architectures, in part due to the appeal of RISC as an architecture that could be taught in a semester-long course. Since graduate students feed the research pipeline, their initial areas of learning frequently define the future research agenda, which remained focused on RISC. Second, VLIW research tended to be driven by instruction traces generated from scientific or numerical applications. These traces are different in two key ways from the average system-wide non-scientific trace: the numerical traces often have more consistent sequential memory access patterns, and the numerical traces often reflect a greater degree of instruction-level parallelism (ILP). Assuming these traces were typical could lead architecture designers to optimize for cases found more rarely in commercial computing workloads. Fred Weber echoed this latter point in a phone interview. Bhandarkar also speculated that the decision to pursue VLIW was driven by the prejudices of a few researchers, rather than by sound technical analysis.<p><a href="http://courses.cs.washington.edu/courses/csep590/06au/projects/history-64-bit.pdf" rel="nofollow">http://courses.cs.washington.edu/courses/csep590/06au/projec...</a>
> <a href="http://courses.cs.washington.edu/courses/csep590/06au/projects/history-64-bit.pdf" rel="nofollow">http://courses.cs.washington.edu/courses/csep590/06au/projec...</a><p>This link requires a log-in.
It's doubly funny knowing that basically nobody bothers doing these kinds of workloads on CPU if they can help it. And everything you have to do to get GPU floating point performance also makes GPUs really, really bad for normal CPU code. Hell, at one point AMD actually was shipping VLIW for shader code...
> It's doubly funny knowing that basically nobody bothers doing these kinds of workloads on CPU if they can help it.<p>When the Itanium was developed and introduced (2001), nobody was thinking about general-purpose computations. DirectX 8.0, which introduced Shader Model 1.1 (which was far away from being suitable for GPGPU; Shader Model 1.1 was rather about strongly (also size-)limited programs for the vertex and pixel processing stage), was only introduced in 2000, the first release of CUDA was in 2007, and the first release of OpenCL was in 2009.
People have tried all kinds of techniques for VLIW, including techniques that are <i>much</i> better than a purpose built AI, AI isn't a magic silver bullet. Fundamentally there's no reason you can't analyse a piece of code to death, and maximally extract parallelism out of it<p>The fundamental issue is that there simply doesn't exist enough information to be able to extract the necessary parallelism without a rewrite, its the same issue as trying to autovectorise. You can do it to some degree, but it doesn't work in practice to be able to fill out a very wide architecture with reasonable efficacy<p>The SIMT programming model has proven to be much more successful vs trying to autovectorise or mash things into a VLIW architecture
From memory, Glasgow University CS had serious buy in to VLIW models of computation for a while, predating Itanium. There was good reason for believing it might have some interesting behaviours. I think they worked on languages targetting it, data models, things like reversible computation, long lived processes.
It was neat to live through the era where CPUs constantly got faster and they were willing to try such oddball stuff.<p>For such a long time it became “faster and more cores, don’t be different” and just didn’t seem as interesting.<p>Apple Silicon had been very interesting to me. I’m really hoping to see a stronger ARM push on Windows, both because I know it can be great and because it’s just <i>interesting</i>. Windows has never had to switch architectures (for consumers) or support two at once for any reasonable population.<p>Also, whatever happened to mill? We used to get posts about them all the time.<p>And I wonder what would have happened to Power if they had the 3rd party fabs that exist today instead of being stuck with what IBM could make in-house.
I think it died before that, it was just that buried it then.
Even if the magical Itanium compiler did exist, Itanium would have still lost to AMD64. As soon as you introduce anything that doesn't behave in a statically predictable manner (multitasking, or virtualization, or even an application that processes unpredictable input like a web backend or database), your performance drops down to a fraction of what a similarly priced AMD64 chip could do. VLIW is great for some very specific workloads like HPC, but Intel should have never tried to replace x86 with it.
> Ironically, it died around the time LLMs/AI started becoming good.<p>What?<p>I think maybe you are confusing Itanium with something else?<p>Development on itanium stopped in 2013:<p>> On 31 January 2013 Intel issued an update to their plans for Kittson: it would have the same LGA1248 socket and 32 nm process as Poulson, thus effectively halting any further development of Itanium processors.[1]<p>It's true that it shipped until 2021, but I think you had to already have previous orders to get that.<p>[1]<a href="https://en.wikipedia.org/wiki/Itanium" rel="nofollow">https://en.wikipedia.org/wiki/Itanium</a>
Itanium was effectively dead once Intel adopted AMD's x86-64. It just remained a zombie for another 15+ years.
[dead]