Excellent find, an academic paper announcing the book is here<p><a href="https://peer.asee.org/57147.pdf" rel="nofollow">https://peer.asee.org/57147.pdf</a><p>Harris and Harris (no relation) have an excellent book on digital design using RISC-V as the domain problem, <a href="https://pages.hmc.edu/harris/ddca/ddcarv.html" rel="nofollow">https://pages.hmc.edu/harris/ddca/ddcarv.html</a><p><a href="https://pages.hmc.edu/harris/ddca/" rel="nofollow">https://pages.hmc.edu/harris/ddca/</a><p>Their books are <i>perfect</i>, and I hope this textbook gets adopted by thousands of colleges. Our RISC-V future is bright, now we need one on SoC bringup and getting your OS running on that SoC.
Based on description it doesn't sound like SoC design, it sounds like a book about RISC-V microprocessors. To the untrained eye, that sounds similar, but a microprocessor is one part of an SoC, and sometimes it can be a very small part based off the role the microprocessor plays.
Disclaimer up front: I've only read ~10/23 RVSoC draft chapters that were made available as a part of SP2025 E154, so don't take me as any kind of authority on the remaining 13, which I can't wait to get my hands on!<p>In the preface on xx-xxi:<p>```<p>This book took three years of development and another year of production.
There are many more important topics in computer architecture and SoC
design that were omitted from this edition for schedule reasons; we hope
to address them in a future volume:<p>* Multicore<p><pre><code> * Multilevel cache coherency
* Synchronization
* Interprocessor communication
</code></pre>
* Microarchitecture<p><pre><code> * Superscalar
* Out-of-order
* Deeper pipelines
</code></pre>
* RISC-V Extensions<p><pre><code> * Vector
* Hypervisor
* Debug
* Trace
</code></pre>
* Verification<p><pre><code> * Functional coverage metrics
* Hardware emulation
</code></pre>
* SoC Design<p><pre><code> * Intellectual property block design and integration
* AXI interfaces
* Accelerators
* Memory controllers
* Network-on-chip
</code></pre>
* SoC Implementation<p><pre><code> * Timing and power optimization
* Clock gating
* Clock domain crossings
* External interfaces
</code></pre>
```<p>It's definitely processor-centric but I wouldn't say "about RISC-V microprocessors" catches it either. The book is certainly structured around the core, but arguably so too is SoC design, at least at an introductory level. RVSoC uses a real SoC design (CORE-V Wally), and each aspect is covered at a length more or less proportionate to the complexity of its implementation in Wally. Admittedly, Wally's peripherals are fewer and simpler than you might find out in the wild. Wally itself is 80-90% core by lines of RTL (horrible complexity metric I know, sorry).<p>Another way to look at the book is that it picks up where Digital Design and Computer Architecture (by the same Harris and Harris) leaves off. DDCA is used to teach the E85 course at Harvey Mudd; RVSoC is used to teach E154 (SoC design). DDCA builds up to a simplified RV32I-subset pipelined core. If RVSoC started with peripherals without fully elaborating the core, it would leave both readers of both books and students of both courses with a gap in coverage on core design compared to the depth of the remainder of both books.<p>Both are very detailed. With RVSoC at 859 pages in print and 1135 after the digital supplement, the core-related chapters are not by any means stealing airtime from the other components of the SoC, you could strip out every core-related page and still have a modestly-sized textbook. While not by any means an encyclopedic reference for SoC design, I found it to be a wonderful bridge from more elaborated microarchitecture into SoC.<p>I hope they are able to get that future volume out!<p>(edit: quote formatting)
A couple of sample chapters are available here <a href="https://pages.hmc.edu/harris/ddca/rvsocd.html" rel="nofollow">https://pages.hmc.edu/harris/ddca/rvsocd.html</a>
Judging by the authors, I'm sure the book will be excellent. Hopefully it will be available through O'Reilly Online, because the price is a bit steep.
What are some good books/resources on overall System-On-Chip Design?<p>There is a surprising paucity of material on SoC design which are comprehensive and complete. Application-specific tailored features, Cost, Performance, Area, Power etc. all go into SoC design and yet there does not seem to be a comprehensive resource bringing everything together. Even wikipedia isn't detailed enough - <a href="https://en.wikipedia.org/wiki/System_on_a_chip" rel="nofollow">https://en.wikipedia.org/wiki/System_on_a_chip</a><p>I know of only two decent books viz. <i>Computer System Design: System-on-Chip by Michael Flynn and Wayne Luk</i> (this is pretty good) and the older <i>ARM System-on-Chip Architecture by Steve Furber</i>.
You know what. I feel like it’s a fair price.
Ooof. €109.70 in paperback
You can get it direct from Elsevier for ~78 euros: <a href="https://shop.elsevier.com/books/risc-v-system-on-chip-design/harris/978-0-323-99498-9" rel="nofollow">https://shop.elsevier.com/books/risc-v-system-on-chip-design...</a>
I just pre-ordered this book and think it's definitely worth it.<p>Full disclosure: I have no affiliation with the author, but I'm sharing because I genuinely believe in the work.
[dead]
Everything RISC-V is good (even the mistakes which is making it more robust and more mature).
I like RISC-V (it's been my job for the last 7 years) but this is nonsense. Not everything RISC-V is good. CLIC was awful (thankfully it has been abandoned). The spec is not especially well written - the style is inconsistent due to being written by many authors, and it is waaaay too much of a textbook rather than a proper spec. (There is some ongoing work to improve this tbf.)<p>There's a practically unending list of undefined/implementation defined behaviours, which is great if you want to implement an ultra minimal microcontroller with 100 flops, but pretty awful otherwise.<p>Requiring the C (compressed) extension in the RVA profiles was definitely a mistake. The lack of true 16/64kB pages and conditional moves are probably a mistake (though fixable).<p>I don't know how any of these make it more robust and mature.<p>(But to be clear, I still think it's pretty good overall.)
I broadly agree with your points except one.<p>Requiring C (compressed) is necessary to avoid splitting the Linux ecosystem. Chips lacking C would never be able to run binaries compiled with C. There's no practical way for such binaries to detect this and work around it at runtime as they can with other extensions. And emulation would be super-slow given a large proportion of instructions are compressed.<p>Also the excuse given by Qualcomm - that it would make all instructions fixed length and so much easier to decode - is just wrong. RISC-V supports variable length instructions, even much longer than 32 bits, and you've just got to deal with it. Just because Qualcomm acquired a company with a microarchitecture that could only deal with fixed length instructions is no reason to break the ecosystem.<p>Also interested in the problems you see in Zicond. It claims at least to give you most of the benefit of conditional moves using only two instructions, but I've not actually tried using it. (<a href="https://docs.riscv.org/reference/isa/extensions/zicond/_attachments/riscv-zicond.pdf" rel="nofollow">https://docs.riscv.org/reference/isa/extensions/zicond/_atta...</a>)
> Requiring C (compressed) is necessary to avoid splitting the Linux ecosystem. Chips lacking C would never be able to run binaries compiled with C.<p>Yes that's precisely the point of excluding it from the RVA profiles. It would mean that Linux distros <i>don't</i> compile code with C enabled, so chips are free to not support C and therefore can achieve higher performance (probably). And it opens 3/4 of the instruction encoding space for use by other things.<p>> Also the excuse given by Qualcomm - that it would make all instructions fixed length and so much easier to decode - is just wrong. RISC-V supports variable length instructions, even much longer than 32 bits, and you've just got to deal with it.<p>It's not wrong. RISC-V defines a mechanism by which 48/64 bit instructions might be used, but currently none are actually defined. All existing instructions are 16 or 32 bits. Without C all instructions are 32 bits. You don't have to deal with 48 bit instructions because there aren't any.<p>It's possible that they will add some in future, but I'm doubtful of that because a) it would be a huge pain, and b) they didn't for Vector which is where it would have been most useful.<p>> Just because Qualcomm acquired a company with a microarchitecture that could only deal with fixed length instructions is no reason to break the ecosystem.<p>Yeah it was too late to change but that doesn't mean it wasn't a mistake.<p>Zicond looks good - I forgot that exists.
> Yes that's precisely the point of excluding it from the RVA profiles. It would mean that Linux distros don't compile code with C enabled, so chips are free to not support C and therefore can achieve higher performance (probably). And it opens 3/4 of the instruction encoding space for use by other things.<p>The debate was between 16/32/48/64-bit instructions vs naturally aligned 32-bit and 64-bit instructions + new more complex instructions that require cracking to regain code size (things like load/store pair).<p>> RISC-V defines a mechanism by which 48/64 bit instructions might be used, but currently none are actually defined<p>The long-instruction-SIG just started a few weeks ago, and they are working on defining 48/64-bit encodings for instructions that could be used in future RVA profiles (so with high perf implementations in mind). If you are knowledgeable about this stuff, please get involved, so they don't mess it up. (not "you" specifically, but in general)
Compressed is necessary to reduce code size which is important for performance.<p>A bunch of vendors have done high performance server chips which support compressed (Rivos, Ventana, some Chinese vendors), so in actual reality this was only a problem for Qualcomm. And that's only because Qualcomm bought Nuvia and they wanted to do the cheap thing (minimally change the front end) rather than the right thing.
> RISC-V supports variable length instructions, even much longer than 32 bits, and you've just got to deal with it.<p>...no, not really? There is nothing like 9 byte-long MOVABS instruction of x64 that exists on RISC-V.<p>The main difficulty in decoding is that 32-bit instructions are not required to be 4-byte aligned, this means that naïve decoders will spend 2 cycles fetching such split instructions. It's possible to add a 4-byte ring buffer but all in all, efficiently supporting the C extension is non-trivial.
RISC-V definitely does support instructions longer than 32 bits, starting at 48 bits (ie. 32 + 16), and going much longer. They <i>are</i> much easier to decode than x86 because the length is evident from the first byte. No ratified extension uses them now, but you're going to need to deal with them as the extension space gets more crowded. Including dealing with instructions split across cache lines and pages, and instructions aligned to 16 bits.<p>I'm not sure what point you're making TBH.
My point is that fixed-length instructions are supposed to be easier to decode than variable-length ones, right?<p>If not, then why even bother with fitting immediates and inventing LUI/AUIPC, just have a 48-bit long LI instruction. The same goes for 64-bit, an 80-bit LI.W is still shorter than the piecemeal construction with several instructions.<p>If yes, then the small cores are arbitrarily given a burden of supporting variable-length instructions, supposedly efficiently: if your instruction fetch is 16-bit wide, you need two fetches to fetch a single 32-bit instruction, which sucks; if it's 32-bit wide, you need to conditionally stash the upper half for the next fetch cycle, and still prefetch yet more 32-bits because that upper half may contain only a half of a full 32-bit instruction; alternatively, you can fetch 32-bits at alternated aligned/misaligned addresses and ignore the inefficiency of throwing away re-fetched bits — again, all of this sucks.
Yes, fixed-length instructions are easier to decode, but that also means a hard upper limit on the number of instructions that could ever be supported. Which is obviously a problem for a future-proof architecture.<p>The rationale for this and also for confining the base set to 32 bit is explained here: <a href="https://docs.riscv.org/reference/isa/v20250508/unpriv/extending.html#35-2-risc-v-extension-design-philosophy" rel="nofollow">https://docs.riscv.org/reference/isa/v20250508/unpriv/extend...</a>
I've read that rationale, and it's, well, I'm not going to say it's <i>lying</i>, but it's <i>insincere</i>. By the time it was written, they already settled on 16-bit alignment, and fetching (and then decoding) 16-bit aligned 32-bit instructions is either inefficient, or hard, or requires extra circuitry (or an instruction cache).
High performance RISC-V chips exist from Rivos, Ventana and others, and high performance variable length chips also exist in general (AMD, Intel). So in actual reality it increases complexity somewhat, but is not a problem.