Aegis – open-source FPGA silicon

4 comments

• mosaibah57 minutes ago
  The gap this closes is real. IceStorm and Apicula gave you open tooling but you were still loading bitstreams onto someone else's closed fabric. Yosys/nextpnr same story. Aegis is the first time the fabric itself is auditable, which matters a lot for anyone building hardware that needs a complete trust chain from RTL down to GDS. The wafer.space + open PDK path makes it actually tapeout-able, not just a simulation exercise. Curious how the LUT4 fabric competes on density against GF180 commercial offerings, that's usually where open implementations get humbling
• dizhn2 hours ago
  There's also an open source Authenticator software with the same name.
• Bluebirt4 hours ago
  Neat project - there are already a couple of good open FPGA projects. Have a look at Dirk Koch&#x27;s and the FABolous teams work. They are doing exceptional work.<p>But all open FPGA projects miss the IO required for a good design. They do not have any serdes hardware nor DDR IO cells.
  • LarsKrimi4 hours ago
    This project seems to have a serdes block which seems to wrap whatever is in the PDK. Didn&#x27;t look too far down but from a cursory glance it looked like it was built for an internal clock of 50 MHz (clock default to 20 ns) with an oversampling of 8: 400 MHz<p>If those numbers are at all right it puts it in useful territory. Very much so for a first spin<p>For a first spin it looks overall pretty useful. The only nitpick I have would be that `operation` on the DSP tile should be from fabric instead of config (hardcoded in bitstream) otherwise I don&#x27;t see a convenient way of resetting the accumulator(?)
  • __patchbit__4 hours ago
    [flagged]
• blowback5 hours ago
  Excellent. Put me down for a couple.