Looks like the author have not used software pipelining compiler directives with the kernel loops. AMD AIE architecture has 5 cycle load/store latency and 7 cycle FP unit latency. With software pipelining, they could have 5-10x speed up for long loops.
This architecture is likely going to be a dead end for AMD. It has been in the wild for several years, yet still has no open programming model, multiple compiler stacks with poor software support. I find it likely that AMD drops this architecture and unifies their ML support around their GPGPU hardware.
Note that this is BLAS on the AMD/Xilinx VCK5000 FPGA: <a href="https://www.amd.com/en/products/adaptive-socs-and-fpgas/evaluation-boards/vck5000.html" rel="nofollow">https://www.amd.com/en/products/adaptive-socs-and-fpgas/eval...</a>
So it's called an "AI Engine", but its performance is worse than just running the same thing on CPU? Doesn't it make it essentially useless for anything AI related? What's the point of this hardware then? Better power efficiency for tiny models? Surely someone must be using it for something?
The point is offloading ML workloads to hardware that is energy efficient, not necessarily "fast" hardware.<p>You want to minimize the real and energy costs at the expense of time.<p>Assuming NPUs don't get pulled from consumer hardware altogether, theoretically the time/efficiency trade-off gap will become smaller and smaller as time goes on.
The CPU baseline seems to be the beefy host CPU. The AIE is presumably faster than what you could do with the FPGA (DPS, LUT, etc.) alone.