> x86 is unusual in mostly having a maximum of two operands per instruction[2]<p>Perhaps interesting for those who aren't up to date, the new APX extension allows 3-operand versions of most of the ALU instructions with a new data destination, so we don't need to use temporary registers - making them more RISC-like.<p>The downside is they're EVEX encoded, which adds a 4-byte prefix to the instruction.<p><a href="https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html" rel="nofollow">https://www.intel.com/content/www/us/en/developer/articles/t...</a>
> <i>Using `lea` […] is useful if both of the operands are still needed later on in other calculations (as it leaves them unchanged)</i><p>As well as making it possible to preserve the values of both operands, it’s also occasionally useful to use `lea` instead of `add` because it preserves the CPU flags.
This guy is tricking us into learning assembly! Get 'em!!
As a side note of appreciation, I think that we can't do better than what he did for being transparent that LLM was used but still just for the proof-reading.
Agreed that it's nice he acknowledged it, but proof reading is about as innocuous of a task for LLMs as they come. Because you actually wrote the content and know its meaning (or at least intended meaning), you can instantly tell when to discard anything irrelevant from the LLM. At worst, it's no better than just skipping that review step.
It does make me curious about the what the super anti-ai people will do.<p>Matt Godbolt is, obviously, <i>extremely</i> smart and has a lot of interesting insight as a domain expert. <i>But</i>... this was LLM-assisted.<p>So, anyone who has previously said they'll never (knowingly) read anything that an ai has touched (or similar sentiment) are you going to skip this series? Make an exception?
I think most people wouldn't call proof-reading 'assistance'. As in, if I ask a colleague to review my PR, I wouldn't say he assisted me.<p>I've been throwing my PR diffs at Claude over the last few weeks. It spits a <i>lot</i> of useless or straight up wrong stuff, but sometimes among the insanity it manages to get one or another typo that a human missed, and between letting a bug pass or spending extra 10m per PR going through the nothingburguers Claude throws at me, I'd rather lose the 10m.
This triggers a vague memory of trying to figure out why my assembler (masm?) was outputting a LEA instead of a MOV. I can't remember why. Maybe LEA was more efficient, or MOV didn't really support the addressing mode and the assembler just quietly fixed it for you.<p>In any case, I felt slightly betrayed by the assembler for silently outputting something I didn't tell it to.
LEA and MOV are doing different things. LEA is just calculating the effective address, but MOV calculates the address then retrieves the value stored at that address.<p>e.g. If base + (index * scale) + offset = 42, and the value at address 42 is 3, then:<p>LEA rax, [base + index * scale + offset] will set rax = 42<p>MOV rax, [base + index * scale + offset] will set rax = 3
Loving this series! I'm currently implementing a z80 emulator (gameboy) and it's my first real introduction to CISC, and is really pushing my assembly / machine code skills - so having these blog posts coming from the "other direction" are really interesting and give me some good context.<p>I've implemented toy languages and bytecode compilers/vms before but seeing it from a professional perspective is just fascinating.<p>That being said it was totally unexpected to find out we can use "addresses" for addition on x86.
A seasoned C programmer knows that "&arr[index]" is really just "arr + index" :) So in a sense, the optimizer rewrote "x + y" into "(int)&(((char*)x)[y])", which looks scarier in C, I admit.
The text mentions that it can also do multiplication but doesn't expand on that.<p>E.g. for x * 5 gcc issues lea eax, [rdi+rdi*4].
It also says the multiplier must be one of 2, 4 or 8.<p>So I guess this trick then only works for multiplication by 2, 3, 4, 5, 8 or 9?
The tricks to avoid multiplication (and division) are probably worth a whole post.<p><pre><code> x * 6:
lea eax, [rdi+rdi*2]
add eax, eax
x * 7:
lea eax, [0+rdi*8]
sub eax, edi
x * 11:
lea eax, [rdi+rdi*4]
lea eax, [rdi+rax*2]
</code></pre>
But with -Os you get imul eax, edi, 6<p>And on modern CPUs multiplication might not be actually all that slow (but there may be fewer multiply units).
LEA is a beautiful example of instruction reuse. Designed for pointer arithmetic, repurposed for efficient addition. It's a reminder that good ISA design leaves room for creative optimization - and that compilers can find patterns human assembly programmers might miss.
Human assembly programmers on the 8086 used LEA all the fucking time. And I'm not sure good ISA design is characterized by the need for ingenious hacks to get the best mileage out of the hardware; rather the opposite, in my view. The ARM2's ISA design is head and shoulders better than the 8086's.
>However, in this case it doesn’t matter; those top bits5 are discarded when the result is written to the 32-bit eax.<p>>Those top bits should be zero, as the ABI requires it: the compiler relies on this here. Try editing the example above to pass and return longs to compare.<p>Sorry, I don't understand. How could the compiler both discard the top bits, and also rely on the top bits being zero? If it's discarding the top bits, it won't matter whether the top bits are zero or not, so it's not relying on that.
(Almost) any instruction on x64 that writes to a 32-bit register as destination, writes the lower 32-bits of the value into the lower 32 bits of the full 64-bit register and zeroes out the upper 32 bits of the full register. He touched on it in his previous note "why xor eax, eax".<p>But the funny thing is, the x64-specific supplement for SysV ABI doesn't actually specify whether the top bits should be zeroes or not (and so, if the compiler could rely on e.g. function returning ints to have upper 32 bits zeroes, or those could be garbage), and historically GCC and Clang diverged in their behaviour.
He's actually wrong on the ABI requiring the top bits to be 0. It only requires that the bottom 32 bits match the parameter, but the top bits of a 32-bit parameter passed in a 64-bit register can be anything (at least on Linux).<p>You can see that in this godbolt example: <a href="https://godbolt.org/z/M1ze74Gh6" rel="nofollow">https://godbolt.org/z/M1ze74Gh6</a><p>The reason the code in his post works is because the upper 32 bits of the parameters going into an addition can't affect the low 32 bits of the result, and he's only storing the low 32 bits.
The LLVM x86-64 ABI requires the top bits to be zero. GCC treats them as undefined. Until a recent clarification, the x86-64 psABI made the upper bits undefined by omission only, which is why I think most people followed the GCC interpretation.<p><a href="https://github.com/llvm/llvm-project/issues/12579" rel="nofollow">https://github.com/llvm/llvm-project/issues/12579</a>
<a href="https://groups.google.com/g/x86-64-abi/c/h7FFh30oS3s/m/Gksanh3WAAAJ" rel="nofollow">https://groups.google.com/g/x86-64-abi/c/h7FFh30oS3s/m/Gksan...</a>
<a href="https://gitlab.com/x86-psABIs/x86-64-ABI/-/merge_requests/61" rel="nofollow">https://gitlab.com/x86-psABIs/x86-64-ABI/-/merge_requests/61</a>
There is something fun about using godbolt.org to say that Matt Godbolt is wrong.
Part of the Advent of Compiler Optimisations <a href="https://xania.org/AoCO2025" rel="nofollow">https://xania.org/AoCO2025</a><p>Loving it so far!
It's still wild to me that "Godbolt" is an actual surname.
> Yesterday we saw how compilers zero registers efficiently.<p>It took several tries to understand <i>zero</i> is a verb
Often I use "zeroize" rather than "zero" to avoid such confusion.
It might have been a <i>little</i> bit clearer to say:<p><pre><code> Yesterday we saw how compilers zero out registers efficiently.
</code></pre>
Or better still:<p><pre><code> Yesterday we saw how compilers set the values in registers to zero efficiently.</code></pre>
Verbing weirds language.
What's the current best resources to learn assembly? So that I can understand output of simple functions. I don't want to learn to write it properly, I just want to be able to understand on what's happening.
<a href="https://godbolt.org/" rel="nofollow">https://godbolt.org/</a><p>You can select the assembly output (I like RISCV but you can pick ARM, x86, mips, etc with your choice of compiler) and write your own simple functions. Then put the original function and the assembly output into an LLM prompt window and ask for a line-by-line explanation.<p>Also very useful to get a copy of Computer Organization and Design RISC-V Edition: The Hardware Software Interface, by Patterson and Hennessy.
Honestly, x86 is not nearly as CISC as those go. It just has a somewhat developed addressing modes comparing to the utterly anemic "register plus constant offset" one, and you are allowed to fold some load-arithmetic-store combinations into a single instruction. But that's it, no double- or triple-indexing or anything like what VAXen had.<p><pre><code> BINOP disp(rd1+rd2 shl #N), rs
vs.
SHL rTMP1, rd2, #N
ADD rTMP1, rTMP1, rd1
LOAD rTMP2, disp(rTMP1)
BINOP rTMP2, rTMP2, rs
STORE disp(rTMP1), rTMP2
</code></pre>
And all it really takes to support this is just adding a second (smaller) ALU on your chip to do addressing calculations.
One of my biggest bugbears in CS instruction is the overdue emphasis on RISC v CISC, especially as there aren't any really good models to show you what the differences are, given the winnowing of ISAs. In John Mashey's infamous posts [1] sort of delineating an ordered list from most RISCy to most CISCy, the architectures that are the most successful have been the ones that really crowded the RISC/CISC line--ARM and x86.<p>It also doesn't help that, since x86 is the main goto example for CISC, people end up not having a strong grasp on what features of x86 make it actually CISC. A lot of people go straight to its prefix encoding structure or its ModR/M encoding structure, but honestly, the latter is pretty much just a "compressed encoding" of RISC-like semantics, and the former is far less insane than most people give it credit for. But x86 <i>does</i> have a few weird, decidedly-CISC instruction semantics in it--these are the string instructions like REP MOVSB. Honestly, take out about a dozen instructions, and you could make a solid argument that modern x86 <i>is</i> a RISC architecture!<p>[1] <a href="https://yarchive.net/comp/risc_definition.html" rel="nofollow">https://yarchive.net/comp/risc_definition.html</a>
There's also a lot of specialized instructions like AES ones.<p>But the main thing that makes x86 CISC to me is not the actual instruction set, but the byte encoding, and the complexity there.
The classic distinction is that a CISC has data processing instructions with memory operands, and in a RISC they only take register parameters. This gets fuzzy though when you look at AArch64 atomic instructions like ldadd which do read-modify-write all in a single instruction.
Eh, that's really just a side effect of almost 50 years of constant evolution from a 8-bit microprocessor. Take look at VAX [0], for instance: its instruction encoding is pretty clean yet it's an actual example of a CISC ISA that was impossible to speed up like, literally: DEC engineers tried very hard and concluded that making a truly pipelined & super-scalar implementation was basically impossible; so DEC had to move to Alpha. See [1] for more from John Mashey.<p>Edit: the very, very compressed TL;DR is that if you do only one memory load (or one memory load + store back into this exact location) per instruction, it scales <i>fine</i>. But the moment you start doing chained loads, with pre- and post-increments which are supposed to write back changed values into the memory and be visible, and you have several memory sources, and your memory model is actually "strong consistency", well, you're in a world of pain.<p>[0] <a href="https://minnie.tuhs.org/CompArch/Resources/webext3.pdf" rel="nofollow">https://minnie.tuhs.org/CompArch/Resources/webext3.pdf</a><p>[1] <a href="https://yarchive.net/comp/vax.html" rel="nofollow">https://yarchive.net/comp/vax.html</a>
Would this matter for performance? You already have so many execution units that are actually difficult to keep fully fed even when decoding instructions and data at the speed of cache.
Do we really know that LEA is using the hardware memory address computation units? What if the CPU frontend just redirects it to the standard integer add units/execution ports? What if the hardware memory address units use those too?<p>It would be weird to have 2 sets of different adders.
> It would be weird to have 2 sets of different adders.<p>Not really. CPUs often have limited address math available separately from the ALU. On simple cores, it looks like a separate incrementer for the Program Counter, on x86 you have a lot of addressing modes that need a little bit of math; having address units for these kinds of things allows more effective pipelining.<p>> Do we really know that LEA is using the hardware memory address computation units?<p>There are ways to confirm. You need an instruction stream that fully loads the ALUs, without fully loading dispatch/commit, so that ALU throughput is the limit on your loop; then if you add an LEA into that instruction stream, it shouldn't increase the cycle count because you're still bottlenecked on ALU throughput and the LEA does address math separately.<p>You <i>might</i> be able to determine if LEAs can be dispatched to the general purpose ALUs if your instruction stream is something like all LEAs... if the throughput is higher than what could be managed with only address units, it must also use ALUs. But you may end up bottlenecked on instruction commit rather than math.
The modern Intel/AMD CPUs have distinct ALUs (arithmetic-logic units, where additions and other integer operations are done; usually between 4 ALUs and 8 ALUs in recent CPUs) and AGUs (address generation units, where the complex addressing modes used in load/store/LEA are computed; usually 3 to 5 AGUs in recent CPUs).<p>Modern CPUs can execute up to between 6 and 10 instructions within a clock cycle, and up to between 3 and 5 of those may be load and store instructions.<p>So they have a set of execution units that allow the concurrent execution of a typical mix of instructions. Because a large fraction of the instructions generate load or store micro-operations, there are dedicated units for address computation, to not interfere with other concurrent operations.
But can the frontend direct these computations based on what's available? If it sees 10 LEA instructions in a row, and it has 5 AGU units, can it dispatch 5 of those LEA instructions to other ALUs?<p>Or is it guaranteed that a LEA instruction will always execute on an AGU, and an ADD instruction always on an ALU?
This can vary from CPU model to CPU model.<p>No recent Intel/AMD CPU executes directly LEA or other instructions, they are decoded into 1 or more micro-operations.<p>The LEA instructions are typically decoded into either 1 or 2 micro-operations. The addressing modes that add 3 components are usually decoded into 2 micro-operations, like also the obsolete 16-bit addressing modes.<p>The AGUs probably have some special forwarding paths for the results towards the load/store units, which do not exist in ALUs. So it is likely that 1 of the up to 2 LEA micro-operations are executed only in AGUs. On the other hand, when there are 2 micro-operations it is likely that 1 of them can be executed in any ALU. It is also possible for the micro-operations generated by a LEA to be different from those of actual load/store instructions, so that they may also be executed in ALUs. This is decided by the CPU designer and it would not be surprising if LEAs are processed differently in various CPU models.
The confusing thing about LEA is that the source operands are within a '[]' block which makes it look like a memory access.<p>I'd love to know why that is.<p>I think the calculation is also done during instruction decode rather than on the ALU, but I could be wrong about that.
It (LEA) does all the work of a memory access (the address computation part) without actually performing the memory access.<p>Instead of reading from memory at "computed address value" it returns "computed address value" to you to use elsewhere.<p>The intent was likely to compute the address values for MOVS/MOVSB/MOVSW/MOVSD/MOVSQ when setting up a REP MOVS (or other repeated string operation). But it turned out they were useful for doing three operand adds as well.
LEA is the equivalent of & in C. It gives you the address of something.<p>Fun question: what does the last line of this do?<p>MOV BP,12
LEA AX,[BP]
MOV BX,34
LEA AX,BX
I think OP was just making a comment on the asymmetry of the syntax. Brackets [] are usually used to dereference.<p>Why is this written<p><pre><code> lea eax, [rdi + rsi]
</code></pre>
instead of just<p><pre><code> lea eax, rdi + rsi
?</code></pre>
It's due to the way the instruction is encoded. `lea` would've needed special treatment in syntax to remove the brackets.<p>In `op reg1, reg2`, the two registers are encoded as 3 bits each the ModRM byte which follows the opcode. Obviously, we can't fit 3 registers in the ModRM byte because it's only 8-bits.<p>In `op reg1, [reg2 + reg3]`, reg1 is encoded in the ModRM byte. The 3 bits that were previously used for reg2 are instead `0b100`, which indicates a SIB byte follows the ModRM byte. The SIB (Scale-Index-Base) byte uses 3 bits each for reg2 and reg3 as the base and index registers.<p>In any other instruction, the SIB byte is used for addressing, so syntax of `lea` is consistent with the way it is encoded.<p>Encoding details of ModRM/SIB are in Volume2, Section 2.1.5 of the ISA manual: <a href="https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html" rel="nofollow">https://www.intel.com/content/www/us/en/developer/articles/t...</a>
When you encode an x86 instruction, your operands amount to either a register name, a memory operand, or an immediate (of several slightly different flavors). I'm no great connoisseur of ISAs, but I believe this basic trichotomy is fairly universal for ISAs. The operands of an LEA instruction are the destination register and a memory operand [1]. LEA happens to be the unique instruction where the memory operand is not dereferenced in some fashion in the course of execution; it doesn't make a lot of sense to create an entirely new syntax that works only for a single instruction.<p>[1] On a hardware level, the ModR/M encoding of most x86 instructions allows you to specify a register operand and either a memory or a register operand. The LEA instruction only allows a register and a memory operand to be specified; if you try to use a register and register operand, it is instead decoded as an illegal instruction.
> LEA happens to be the unique instruction where the memory operand is not dereferenced<p>Not quite unique: the now-deprecated Intel MPX instructions had similar semantics, e.g. BNDCU or BNDMK. BNDLDX/BNDSTX are even weirder as they don't compute the address as specified but treat the index part of the memory operand separately.
The way I rationalize it is that you're getting the address of something. A raw address isn't what you want the address of, so you're doing something like &(*(rdi+rsi)).
Yes, that’s what I meant
LEA stands for Load Effective Address, so the syntax is as-if you're doing a memory access, but you are just getting the calculated address, not reading or writing to that address.<p>LEA would normally be used for things like calculating address of an array element, or doing pointer math.
[dead]