From the article: Lookup tables are always faster than calculation - is that true? I'd think that while in the distant past maybe today due to memory being much slower than CPU the picture is different nowadays. If you're calculating a very expensive function over a small domain so the lookup fits in L1 Cache then I can see it would be faster, but you can do a lot of calculating in the time needed for a single main memory access.
You will need to first sit and ballpark, and then sit and benchmark, and discover your ballpark was probably wrong anyhow:-)<p>Some (for me) useful pointers to that regard for both:<p>1. <a href="https://www.agner.org/optimize/instruction_tables.pdf" rel="nofollow">https://www.agner.org/optimize/instruction_tables.pdf</a> - an extremely nice resource on micro architectural impacts of instructions<p>2. <a href="https://llvm.org/docs/CommandGuide/llvm-mca.html" rel="nofollow">https://llvm.org/docs/CommandGuide/llvm-mca.html</a> - tooling from Intel that allows to see some of these in real machine code<p>3. <a href="https://www.intel.com/content/www/us/en/developer/articles/tool/performance-counter-monitor.html" rel="nofollow">https://www.intel.com/content/www/us/en/developer/articles/t...</a> - shows you whether the above is matching the reality (besides the CPU alone, more often than not your bottleneck <i>is</i> actually memory accesses; at least on the first access which wasn’t triggered by a hardware prefetcher or a hint to it. On Linux it would be staring at “perf top” results.<p>So, the answer is as is very often - “it depends”.
A few more links for low level CPU benchmarking<p>1 - <a href="https://www.uops.info/index.html" rel="nofollow">https://www.uops.info/index.html</a> similar content to Anger's tables<p>2 - <a href="https://reflexive.space/zen2-ibs/" rel="nofollow">https://reflexive.space/zen2-ibs/</a> how to capture per micro op data on AMD >= Zen 1 CPUs<p>I agree on "it depends". And usually not only on your actual code and data, but also how you arrange it over cache lines, what other code on the same core/complex/system is doing to your view of the cache and some other internal CPU features like prefetchers or branch predictors.
...and we always circle back to "premature optimization is the root of all evil", since processors are a wee bit more intelligent with our instructions than we thought. :)
Not <i>that</i> intelligent. If you have two loads and one store per cycle, then that’s it. (Recall that we have SSDs with 14 GB/s sequential reads now, yet CPU clocks are below 6 GHz.) Most of the computational power of a high-performance CPU is in the vector part; still the CPU won’t try to exploit it if you don’t, and the compiler will try but outside of the simplest cases won’t succeed. (Most of the computational power of a high-performance <i>computer</i> is in the GPU, but I haven’t gotten that deep yet.)<p>I don’t mean to say that inefficient solutions are unacceptable; they have their place. I do mean to say that, for example, for software running on end-users’ computers (including phones), the programmer is hardly entitled to judge the efficiency on the scale of the entire machine—the entire machine does not belong to them.<p>> We <i>should</i> forget about small inefficiences, say 97% of the time; premature optimization is the root of all evil. Yet we should not pass up our opportunities in that critical 3%. A good programmer will not be lulled into complacency by such reasoning, he will be wise to look carefully at the critical code; but only <i>after</i> that code has been identified.<p>D. E. Knuth (1974), “Structured Programming with go to Statements”, <i>ACM Comput. Surv.</i> 6(4).
You are right, but with a good optimizing compiler and out of order execution, your code will not work the way you guess most of the time, even though it accomplishes what you want.<p>On the other hand, while doing high performance compute, the processor will try to act smart to keep everything saturated. As a result, you still need to look at cache trash ratio, IPC, retirement ratio, etc. to see whether you are using the system at its peak performance, and again CPU is doing its thing to keep the numbers high, but that's not enough of course. You have to do your own part and write good code.<p>In these cases where you share the machine (which can be a cluster node or a mobile phone), maximizing this performance is again beneficial since it allows smoother operation both for your and other users' code in general. Trying to saturate the system with your process is a completely different thing, but you don't have to do that to have nice and performant code.<p>GPU computation is nice, and you can do big things fast, but it's not suitable for optimizing and offloading every kind of task, and even if though the task is suitable for the GPU, the scale of the computation still matters, because a competent programmer can fit billions of computations until a GPU starts running your kernel. The overhead is just too big.<p>Knuth's full quote doesn't actually invalidate me, because that's how I operate while writing code, designed for high performance or not.
And so the line continues<p><a href="https://hn.algolia.com/?dateRange=all&page=0&prefix=false&query=%22Yet%20we%20should%20not%20pass%20up%20our%20opportunities%20in%20that%20critical%22&sort=byDate&type=comment" rel="nofollow">https://hn.algolia.com/?dateRange=all&page=0&prefix=false&qu...</a>
> Lookup tables are always faster than calculation - is that true?<p>Maybe on the Z80. Contemporary RAM was quite fast compared to it, by our sad standards.<p>A table lookup per byte will see you hit a pretty hard limit of about 1 cycle per byte on all x86 CPUs of the last decade. If you’re doing a state machine or a multistage table[1] where the next table index depends on both the next byte and the previous table value, you’ll be lucky to see half that. Outracing your SSD[2] you’re not, with this approach.<p>If instead you can load a 64-bit chunk (or several!) at a time, you’ll have quite a bit of leeway to do some computation to it before you’re losing to the lookup table, especially considering you’ve got fast shifts and even multiplies (another difference from the Z80). And if you’re doing 128- or 256-bit vectors, you’ve got even more compute budget—but you’re also going to spend a good portion of it just shuffling the right bytes into the right positions. Ultimately, though, one of your best tools there is going to be ... an instruction that does 16 resp. 32 lookups in a 16-entry table at a time[3].<p>So no, if you want to be fast on longer pieces of data, in-memory tables are not your friend. On smaller data, with just a couple of lookups, they could be[4]. In any case, you need to be thinking about your code’s performance in detail for these things to matter—I can’t think of a situation where “prefer a lookup table” is a useful heuristic. “Consider a lookup table” (then measure), maybe.<p>[1] <a href="https://www.unicode.org/versions/latest/ch05.pdf" rel="nofollow">https://www.unicode.org/versions/latest/ch05.pdf</a><p>[2] <a href="https://lemire.me/en/talk/perfsummit2020/" rel="nofollow">https://lemire.me/en/talk/perfsummit2020/</a><p>[3] <a href="http://0x80.pl/notesen/2008-05-24-sse-popcount.html" rel="nofollow">http://0x80.pl/notesen/2008-05-24-sse-popcount.html</a><p>[4] <a href="https://tia.mat.br/posts/2014/06/23/integer_to_string_conversion.html" rel="nofollow">https://tia.mat.br/posts/2014/06/23/integer_to_string_conver...</a>
On the Z80 any memory access had a fixed cost of 3 clock cycles (in reality the memory system could inject wait cycles, but that was an esoteric case). Together with the instruction fetch of 4 clock cycles the fastest instruction to load an 8-bit value from an address that's already in a 16-bit register (like LD A,(HL)) takes 7 clock cycles.<p>The fastest instructions that didn't access memory (like adding two 8-bit registers) were 4 clock cycles, so there's really not much room to beat a memory access with computation.<p>Today "it depends", I still use lookup tables in some places in my home computer emulators, but only after benchmarking showed that the table is actually slightly faster.
Depends on the hardware and what you are making with that hardware. Some processors can do complicated things stupidly fast (e.g. when SIMD done right), and for some hardware platforms, a mundane operation can be very costly since they are designed for other things primarily.<p>My favorite story is an embedded processor which I forgot its ISA. The gist was, there was a time budget, and doing a normal memory access would consume 90% of that budget alone. The trick was to use the obscure DMA engine to pump data into the processor caches asynchronously. This way, moving data was only ~4% of the same budget, and they have beaten their performance targets by a large margin.
The article does mention cache friendly access patterns in the same context.<p>But yes, you're right. Back when I started with optimizations in the mid 90s memory _latencies_ were fairly minor compared to complex instructions so most things that wasn't additions (and multiplications on the Pentium) would be faster from a lookup table, over time memory latencies grew and grew as clock speeds and other improvements made the distance to the physical memory an actual factor and lookup tables less useful compared to recomputing things.<p>Still today there are things that are expensive enough that can be fit in a lookup table that is small enough that it doesn't get evicted from cache during computation, but they're few.
In this case, the lookup table is used for popcount, and there's a comment in the Z80 assembly that says "One lookup vs eight bit tests." If the code could make use of a hardware popcount instruction, the lookup table would lose, but if that isn't available, a 256-byte lookup table could be faster. So it's less "lookup tables are always faster" and more "lookup tables can be faster, this is one such case."
probably fastest popcount in z80 that does not use aligned table, would be shift A through flag, then conditional INC C, unrolled, still slower than ld l,a: ld b,(hl).
> Lookup tables are always faster than calculation - is that true?<p>I know it's not always true on the Nintendo 64, because it shared a single bus between the RAM and "GPU": <a href="https://youtu.be/t_rzYnXEQlE?t=94" rel="nofollow">https://youtu.be/t_rzYnXEQlE?t=94</a>, <a href="https://youtu.be/Ca1hHC2EctY?t=827" rel="nofollow">https://youtu.be/Ca1hHC2EctY?t=827</a>
You are correct and I've even ran into a situation where build-time evaluation was slower than runtime calculation, thanks to code size.
I'm a sometimes CPU architect and came here to argue just this - modern CPUs have far far slower memory access (in clocks) than z80 memory access. To be fair you can probably fit any z80 table you're using into modern L1 cache, but even so you're looking at multiple clocks rather than 1.